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45 dB Digitally Controlled VGA LF to 600 MHz AD8369*
FEATURES Digitally Controlled Variable Gain in 3 dB Steps -5 dB to +40 dB (RL = 1 k ) -10 dB to +35 dB (RL = 200 ) Less than 0.2 dB Flatness over a +20 MHz Bandwidth up to 380 MHz 4-Bit Parallel or 3-Wire Serial Interface Differential 200 Input and Output Impedance Single 3.0 V-5.5 V Supply Draws 37 mA at 5 V Power-Down <1 mA Maximum APPLICATIONS Cellular/PCS Base Stations IF Sampling Receivers Fixed Wireless Access Wireline Modems Instrumentation FUNCTIONAL BLOCK DIAGRAM
BIT3 BIT2 BIT1 BIT0 VPOS PWUP FILT OPHI Gm CELLS OPLO
DENB SENB
GAIN CODE DECODE
3dB STEP
BIAS
INHI CMDC INLO COMM COMM
PRODUCT DESCRIPTION
The AD8369 is a high performance digitally controlled variable gain amplifier (VGA) for use from low frequencies to a -3 dB frequency of 600 MHz at all gain codes. The AD8369 delivers excellent distortion performance: the two-tone, third-order intermodulation distortion is -69 dBc at 70 MHz for a 1 V p-p composite output into a 1 kW load. The AD8369 has a nominal noise figure of 7 dB when at maximum gain, then increases with decreasing gain. Output IP3 is +19.5 dBm at 70 MHz into a 1 kW load and remains fairly constant over the gain range. The signal input is applied to pins INHI and INLO. Variable gain is achieved via two methods. The 6 dB gain steps are implemented using a discrete X-AMP(R) structure, in which the input signal is progressively attenuated by a 200 W R-2R ladder network that also sets the input impedance; the 3 dB steps are implemented at the output of the amplifier. This combination provides very accurate 3 dB gain steps over a span of 45 dB. The output impedance is set by on-chip resistors across the differential output pins,
OPHI and OPLO. The overall gain depends upon the source and load impedances due to the resistive nature of the input and output ports. Digital control of the AD8369 is achieved using either a serial or a parallel interface. The mode of digital control is selected by connecting a single pin (SENB) to ground or the positive supply. Digital control pins can be driven with standard CMOS logic levels. The AD8369 may be powered on or off by a logic level applied to the PWUP pin. For a logic high, the chip powers up rapidly to its nominal quiescent current of 37 mA at 25C. When low, the total dissipation drops to less than a few milliwatts. The AD8369 is fabricated on an Analog Devices proprietary, high performance 25 GHz silicon bipolar IC process and is available in a 16-lead TSSOP package for the industrial temperature range of -40C to +85C. A populated evaluation board is available.
*Patents Pending
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2002 Analog Devices, Inc. All rights reserved.
(V = V, T = 25 noted.) AD8369-SPECIFICATIONS unless5 otherwise C, R = 200
S S
, RL = 1000
, Frequency = 70 MHz, at maximum gain,
Parameter OVERALL FUNCTION Frequency Range GAIN CONTROL INTERFACE Voltage Gain Span Maximum Gain Minimum Gain Gain Step Size Gain Step Accuracy Gain Step Response Time INPUT STAGE Input Resistance Input Capacitance
Conditions 3 dB Bandwidth
Min LF*
Typ
Max 600
Unit MHz dB dB dB dB dB ns W W pF pF nV//Hz V V W W pF pF V V/ms
All bits high (1 1 1 1) All bits low (0 0 0 0) Over entire gain range, with respect to 3 dB step Step = 3 dB, settling to 10% of final value From INHI to INLO From INHI to COMM, from INLO to COMM From INHI to INLO From INHI to COMM, from INLO to COMM
45 40 -5 3 0.05 30 200 100 0.1 1.1 2 1.7 2.2 200 100 0.25 1.5 VS/2 1200 3.0 5.5 42 52 750 1 1.0 2.2
Input Noise Spectral Density Input Common-Mode DC Voltage Measured at pin CMDC Maximum Linear Input |VINHI - VINLO| at Minimum Gain OUTPUT STAGE Output Resistance Output Capacitance Common-Mode DC Voltage Slew Rate POWER INTERFACE Supply Voltage Quiescent Current vs. Temperature Disable Current vs. Temperature POWER UP INTERFACE Enable Threshold Disable Threshold Response Time From OPHI to OPLO From OPHI to COMM, from OPLO to COMM From OPHI to OPLO From OPHI to COMM, from OPLO to COMM No input signal Output step = 1 V
PWUP high -40C TA 85C PWUP low -40C TA 85C Pin PWUP
37 400
V mA mA mA mA V V ms mA
Input Bias Current DIGITAL INTERFACE
Time delay following low to high transition on PWUP until output settles to within 10% of final value PWUP = 5 V Pins SENB, BIT0, BIT1, BIT2, BIT3, and DENB
7
160
Low Condition High Condition Input Bias Current Frequency = 10 MHz Voltage Gain Gain Flatness Noise Figure Output IP3 IMD3 Harmonic Distortion P1dB
2.0 3.0 Low input 150 40.5 +0.05* 7.0 +22 +22 -74 -72 -71 +3 +3
V V mA dB dB dB dBV rms dBm dBc dBc dBc dBV rms dBm
Within 10 MHz of 10 MHz f1 = 9.945 MHz, f2 = 10.550 MHz f1 = 9.945 MHz, f2 = 10.550 MHz VOPHI - VOPLO = 1 V p-p composite Second-Order, VOPHI - VOPLO = 1 V p-p Third-Order, VOPHI - VOPLO = 1 V p-p For 1 dB deviation from linear gain
*The low frequency high-pass corner is determined by the capacitor on pin FILT, C FILT. See the Theory of Operation section for details.
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SPECIFICATIONS (Continued)
Parameter Frequency = 70 MHz Voltage Gain Gain Flatness Noise Figure Output IP3 IMD3 Harmonic Distortion P1dB Frequency = 140 MHz Voltage Gain Gain Flatness Noise Figure Output IP3 IMD3 Harmonic Distortion P1dB Frequency = 190 MHz Voltage Gain Gain Flatness Noise Figure Output IP3 IMD3 Harmonic Distortion P1dB Frequency = 240 MHz Voltage Gain Gain Flatness Noise Figure Output IP3 IMD3 Harmonic Distortion P1dB Frequency = 320 MHz Voltage Gain Gain Flatness Noise Figure Output IP3 IMD3 Harmonic Distortion P1dB REV. 0 Conditions Min Typ 40.5 0.1 7.0 +19.5 +19.5 -69 -68 -64 +3 +3 40.0 0.10 7.0 +17 +17 -64 -63 -55 +3 +3 39.7 0.1 7.2 +15.5 +15.5 -61 -57 -51 +2 +2 39.3 0.1 7.2 +14 +14 -58 -50 -49 +1.5 +1.5 39.0 0.15 7.4 +11.5 +11.5 -53 -47 -49 +1.0 +1.0 Max Within 20 MHz of 70 MHz f1 = 69.3 MHz, f2 = 70.7 MHz f1 = 69.3 MHz, f2 = 70.7 MHz VOPHI - VOPLO = 1 V p-p composite Second-Order, VOPHI - VOPLO = 1 V p-p Third-Order, VOPHI - VOPLO = 1 V p-p For 1 dB deviation from linear gain
AD8369
Unit dB dB dB dBV rms dBm dBc dBc dBc dBV rms dBm dB dB dB dBV rms dBm dBc dBc dBc dBV rms dBm dB dB dB dBV rms dBm dBc dBc dBc dBV rms dBm dB dB dB dBV rms dBm dBc dBc dBc dBV rms dBm dB dB dB dBV rms dBm dBc dBc dBc dBV rms dBm
Within 20 MHz of 140 MHz f1 = 139.55 MHz, f2 = 140.45 MHz f1 = 139.55 MHz, f2 = 140.45 MHz VOPHI - VOPLO = 1 V p-p composite Second-Order, VOPHI - VOPLO = 1 V p-p Third-Order, VOPHI - VOPLO = 1 V p-p For 1 dB deviation from linear gain
Within 20 MHz of 190 MHz f1 = 189.55 MHz, f2 = 190.45 MHz f1 = 189.55 MHz, f2 = 190.45 MHz VOPHI - VOPLO = 1 V p-p composite Second-Order, VOPHI - VOPLO = 1 V p-p Third-Order, VOPHI - VOPLO = 1 V p-p For 1 dB deviation from linear gain
Within 20 MHz of 240 MHz f1 = 239.55 MHz, f2 = 240.45 MHz f1 = 239.55 MHz, f2 = 240.45 MHz VOPHI - VOPLO = 1 V p-p composite Second-Order, VOPHI - VOPLO = 1 V p-p Third-Order, VOPHI - VOPLO = 1 V p-p For 1 dB deviation from linear gain
Within 20 MHz of 320 MHz f1 = 319.55 MHz, f2 = 320.45 MHz f1 = 319.55 MHz, f2 = 320.45 MHz VOPHI - VOPLO = 1 V p-p composite Second-Order, VOPHI - VOPLO = 1 V p-p Third-Order, VOPHI - VOPLO = 1 V p-p For 1 dB deviation from linear gain -3-
AD8369 SPECIFICATIONS (Continued)
Parameter Frequency = 380 MHz Voltage Gain Gain Flatness Noise Figure Output IP3 IMD3 Harmonic Distortion P1dB Conditions Min Typ 38.5 0.15 7.8 +8.5 +8.5 -47 -45 -49 +0.5 +0.5 Max Unit dB dB dB dBV rms dBm dBc dBc dBc dBV rms dBm
Within 20 MHz of 380 MHz f1 = 379.55 MHz, f2 = 380.45 MHz f1 = 379.55 MHz, f2 = 380.45 MHz, VOPHI - VOPLO = 1 V p-p composite Second-Order, VOPHI - VOPLO = 1 V p-p Third-Order, VOPHI - VOPLO = 1 V p-p For 1 dB deviation from linear gain
Specifications subject to change without notice.
TIMING SPECIFICATIONS
SERIAL PROGRAMMING TIMING REQUIREMENTS (VS = 5 V, T = 25C)
Parameter Minimum Clock Pulsewidth (TPW) Minimum Clock Period (TCK) Minimum Setup Time Data vs. Clock (TDS) Minimum Setup Time Data Enable vs. Clock (TES) Minimum Hold Time Clock vs. Data Enable (TEH) Minimum Hold Time Data vs. Clock (TDH)
Typ 10 20 2 2 2 4
Unit ns ns ns ns ns ns
PARALLEL PROGRAMMING TIMING REQUIREMENTS (VS = 5 V, T = 25C)
Parameter Minimum Setup Time Data Enable vs. Data (TES) Minimum Hold Time Data Enable vs. Data (TEH) Minimum Data Enable Width (TPW)
Typ 2 2 4
Unit ns ns ns
MSB (BIT3)
TDS
TDH
MSB-1 (BIT2)
DATA (BIT 0)
MSB
MSB-1
MSB-2
LSB
MSB-2 (BIT1)
TPW TCK CLOCK (BIT 1)
LSB (BIT0)
TES
TES DATA ENABLE (DENB) CLOCK DISABLED CLOCK ENABLED DATA IS LATCHED ON LOW-TO-HIGH TRANSITION OF DENB (NOT TO SCALE) TEH CLOCK DISABLED
TEH
TPW
DENB
DATA IS LATCHED ON HIGH-TO-LOW TRANSITION OF DENB
(NOT TO SCALE)
Serial Programming Timing
Parallel Programming Timing
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AD8369
ABSOLUTE MAXIMUM RATINGS* Table I. Typical Voltage Gain vs. Gain Code (VS = 5 V, f = 70 MHz)
Supply Voltage VS, VPOS . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V PWUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS + 200 mV BIT0, BIT1, BIT2, BIT3, DENB, SENB . . . . . . VS + 200 mV Input Voltage, VINHI - VINLO . . . . . . . . . . . . . . . . . . . . . . . . 4 V Input Voltage, VINHI or VINLO with respect to COMM . . 4.5 V Input Voltage, VINHI - VINLO with respect to COMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COMM - 200 mV Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 265 mW JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C/W Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125C Operating Temperature Range . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Lead Temperature Range (soldering 60 sec) . . . . . . . to 300C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Gain Code 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Typical Gain (dB) BIT3 BIT2 BIT1 BIT0 RL = 1 k 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 -5 -2 1 4 7 10 13 16 19 22 25 28 31 34 37 40
Typical Gain (dB) RL = 200 -10 -7 -4 -1 2 5 8 11 14 17 20 23 26 29 32 35
ORDERING GUIDE
Model
Temperature Range
Package Description Tube, 16-Lead TSSOP 7" Tape and Reel Evaluation Board
Package Option RU-16
AD8369ARU -40C to +85C AD8369ARU-REEL7 -40C to +85C AD8369EVAL
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8369 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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AD8369
PIN CONFIGURATION
INLO COMM BIT0 BIT1 BIT2 BIT3 DENB OPLO 1 2 3 4 5 6 7 8 16 INHI 15 COMM
AD8369
TOP VIEW (Not To Scale)
14 PWUP 13 VPOS 12 SENB 11 FILT 10 CMDC 9 OPHI
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 INLO COMM BIT0 BIT1 BIT2 BIT3 DENB OPLO OPHI CMDC FILT SENB VPOS PWUP COMM INHI
Function Balanced Differential Input. Internally biased, should be ac-coupled. Device Common. Connect to low impedance ground. Gain Selection Least Significant Bit. Used as DATA input signal when in serial mode of operation. Gain Selection Control Bit. Used as CLOCK input pin when in serial mode of operation. Gain Selection Control Bit. Inactive when in serial mode of operation. Gain Selection Most Significant Bit. Inactive when in serial mode of operation. Data Enable Pin. Writes data to register. See Timing Specifications for details. Balanced Differential Output. Biased to midsupply, should be ac-coupled. Balanced Differential Output. Biased to midsupply, should be ac-coupled. Common-Mode Decoupling Pin. Connect bypass capacitor to ground for additional common-mode supply decoupling beyond the existing internal decoupling. High-Pass Filter Connection. Used to set high-pass corner frequency. Serial or Parallel Interface Select. Connect SENB to VPOS for serial operation. Connect SENB to COMM for parallel operation. Positive Supply Voltage, VS = +3 V to +5.5 V. Power-Up Pin. Connect PWUP to VPOS to power up the device. Connect PWUP to COMM to power-down. Device Common. Connect to a low impedance ground. Balanced Differential Input. Internally biased, should be ac-coupled.
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Typical Performance Characteristics-AD8369
(VS = 5 V, T = 25 C, RS = 200
50 40
, Maximum gain, unless otherwise noted.)
50 GAIN CODE 15 40 30
30
GAIN - dB
20 RL = 200
GAIN - dB
RL = 1k
20
10 0 10 20 0 1 2 3 4 5 6 78 9 GAIN CODE
10 0 10 20
GAIN CODE 0
10 11 12 13 14 15
10
100 FREQUENCY - MHz
1000
TPC 1. Gain vs. Gain Code at 70 MHz
TPC 4. Gain vs. Frequency by Gain Code, RL = 1 kW
43 41 39 VS = 3V, RL = 1k 37
GAIN - dB GAIN - dB
50 VS = 5V, RL = 1k 40 30 20
GAIN CODE 15
35 33 31
VS = 5V, RL = 200 VS = 3V, RL = 200
10 0
29 27 25 10 100 FREQUENCY - MHz 1000 10 GAIN CODE 0 20 10 100 FREQUENCY - MHz 1000
TPC 2. Maximum Gain vs. Frequency by RL and Supply Voltage
TPC 5. Gain vs. Frequency by Gain Code, RL = 200 W
28 26
21 19
OUTPUT IP3 - dBV rms
35 30
28 23
OUTPUT IP3 - dBm
OUTPUT IP3 - dBm
24 22
17 15
25 20
18 13
20 18
13 11
15
8
10 5 0 10 100 FREQUENCY - MHz 1000
3 -2 -7
16 14 0 1 2 3 4 5 6 78 9 GAIN CODE 10 11 12 13 14 15
9 7
TPC 3. Output IP3 vs. Gain Code at 70 MHz, VS = 5 V, RL = 200 W
TPC 6. Output IP3 vs. Frequency, VS = 5 V, RL = 200 W Maximum Gain
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OUTPUT IP3 - dBV rms
AD8369
-63 -64 -65 -20 -30
OUTPUT IMD - dBc
OUTPUT IMD - dBc
0 1 2 3 4 5 6789 GAIN CODE 10 11 12 13 14 15
-40
-66 -67
-50
-60
-68 -69 -70 -70
-80 0 50 100 150 200 250 300 350 400 450 500 550 600 FREQUENCY - MHz
TPC 7. Two-Tone, IMD3 vs. Gain Code at 70 MHz, VOPHI - VOPLO = 1 V p-p, VS = 5 V, RL = 1 kW
TPC 10. Two-Tone IMD3 vs. Frequency VOPHI - VOPLO = 1 V p-p, VS = 5 V, RL = 1 kW, Maximum Gain
40 45
35 40
HARMONIC DISTORTION - dBc
50 HD3 55 60 65 70 75 0 50 100 150 200 250 FREQUENCY - MHz 300 350 400 HD2
HARMONIC DISTORTION - dBc
45 HD3 50 HD2 55
60
65 70 0 50 100 150 200 250 FREQUENCY - MHz 300 350 400
TPC 8. Harmonic Distortion at VOPHI - VOPLO = 1 V p-p vs. Frequency, VS = 5 V, RL = 1 kW, Maximum Gain
TPC 11. Harmonic Distortion at VOPHI - VOPLO = 1 V p-p vs. Frequency, VS = 5 V, RL = 200 W, Maximum Gain
50
8.0
7.8
40
5V NOISE FIGURE - dB
NOISE FIGURE - dB
7.6 3V 7.4 7.2
30
20
RL = 1k
7.0
10
6.8
0 0 1 2 3 4 5 6 78 9 GAIN CODE 10 11 12 13 14 15
RL = 200
6.6 0 50 100 150 200 250 FREQUENCY - MHz 300 350 400
TPC 9. Noise Figure vs. Gain Code at 70 MHz, VS = 5 V, RL = 200 W
TPC 12. Noise Figure vs. Frequency by RL and Supply Voltage at Maximum Gain
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AD8369
9.0 8.5 8.0 7.5 P1dB - dBm 7.0 6.5 6.0 5.5 5.0 4.5 4.0 0 1 2 3 4 5 6 78 9 GAIN CODE 10 11 12 13 14 15 2.0 1.5 1.0 0.5 P1dB - dBV rms 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 P1dB - dBm 9 8 7 6 5 4 3 2 1 0 10 100 FREQUENCY - MHz 2 1 0 P1dB - dBV rms -1 -2 -3 -4 -5 -6 -7 1000
TPC 13. Output P1dB vs. Gain Code at 70 MHz, VS = 5 V, RL = 200 W
TPC 16. Output P1dB vs. Frequency, VS = 5 V, RL = 200 W, Maximum Gain
80 70
40
50
REVERSE ISOLATION - dB
60 50 40 30 20 10 0 10 100 FREQUENCY - MHz 1000
60
CMRR - dB
70
80
90
100 10 100 FREQUENCY - MHz 1000
TPC 14. Common-Mode Rejection Ratio vs. Frequency at Maximum Gain, VS = 5 V, RL = 200 W (Refer to Appendix for Definition)
TPC 17. Reverse Isolation vs. Frequency at Maximum Gain, VS = 5 V, RL = 200 W (Refer to Appendix for Definition)
250
0.75
250
0.75
R
CAPACITANCE - pF
200
RESISTANCE -
INHI
0.50
200
0.50
C 150
OPHI
150
INLO
0.25
0.25
C 100 10 100 FREQUENCY - MHz 0 1000 100 10
OPLO
100 FREQUENCY - MHz
0 1000
TPC 15. Equivalent Input Resistance and Capacitance vs. Frequency at Maximum Gain
TPC 18. Equivalent Output Resistance and Capacitance vs. Frequency at Maximum Gain
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CAPACITANCE - pF
R
RESISTANCE -
AD8369
90 120 60 120 90 60
150
GAIN CODE 15 750MHz
30
150 750MHz
10MHz 0 380MHz 500MHz 330 210 180
GAIN CODE 15
30
10MHz 0 380MHz
180
GAIN CODES 0, 1, AND 9 210
GAIN CODES 0, 1, AND 9
500MHz
330
240 270
300
240 270
300
TPC 19. Differential Input Reflection Coefficient, S11, ZO = 50 W Differential, Selected Gain Codes
TPC 22. Differential Output Reflection Coefficient, S22, ZO = 50 W Differential, Selected Gain Codes
AVERAGE OF 128 SAMPLES DIFFERENTIAL OUTPUT 250mV/VERTICAL DIVISION
INPUT = 250mV p-p, 10MHz OVERDRIVE
OUTPUT 1V/VERTICAL DIVISION
ZERO ZERO RECOVERY
BIT 0 2V/VERTICAL DIVISION GND TIME - 20ns/DIV
BIT 3 2V/VERTICAL DIVISION GND
TIME - 1 s/DIV
TPC 20. Gain Step Time Domain Response, 3 dB Step, VS = 5 V, RL = 1 kW, Parallel Transparent Mode
TPC 23. Overdrive Recovery, Maximum Gain, VS = 5 V, RL = 1 kW, Parallel Transparent Mode
DIFFERENTIAL OUTPUT 200mV/DIV
DIFFERENTIAL OUTPUT 70MHz, 750mV/DIV ZERO
ZERO
PWUP 2V/VERTICAL DIVISION
INPUT 2mV/DIV GND
GND
TIME - 2 s/DIV
TIME - 20 s/DIV
TPC 21. PWUP Time Domain Response, Maximum Gain, VS = 5 V, RL = 1 kW
TPC 24. Pulse Response, Maximum Gain, VS = 5 V, RL = 1 kW
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AD8369
2.0 1.5 1.0
GAIN ERROR - dB
2.0 1.5 1.0
GAIN ERROR - dB
40 C 0.5 0 0.5 1.0 85 C GAIN ERROR AT 40 C AND 85 C WITH RESPECT TO 25 C. DATA BASED ON 45 PARTS FROM TWO BATCH LOTS. 10 100 FREQUENCY - MHz 1000
0.5 0 0.5 1.0 1.5 2.0 10
40 C
85 C
GAIN ERROR AT 40 C AND 85 C WITH RESPECT TO 25 C. DATA BASED ON 45 PARTS FROM TWO BATCH LOTS. 100 FREQUENCY - MHz 1000
1.5 2.0
TPC 25. Gain Error Due to Temperature Change vs. Frequency, 3 Sigma to Either Side of Mean, VS = 5 V, RL = 1 kW, Maximum Gain
TPC 28. Gain Error Due to Temperature Change vs. Frequency, 3 Sigma to Either Side of Mean, VS = 5 V, RL = 200 W, Maximum Gain
2.0 1.5 1.0
GAIN ERROR - dB
2.0 1.5 1.0
40 C
40 C
0.5 0 0.5 1.0 1.5 2.0 10 100 FREQUENCY - MHz 1000 GAIN ERROR AT 40 C AND 85 C WITH RESPECT TO 25 C. DATA BASED ON 45 PARTS FROM TWO BATCH LOTS. 85 C
GAIN ERROR - dB
0.5 0 0.5 1.0 1.5 2.0 10 100 FREQUENCY - MHz 1000 GAIN ERROR AT 40 C AND 85 C WITH RESPECT TO 25 C. DATA BASED ON 45 PARTS FROM TWO BATCH LOTS.
85 C
TPC 26. Gain Error Due to Temperature Change vs. Frequency, 3 Sigma to Either Side of Mean, VS = 3 V, RL = 1 kW, Maximum Gain
TPC 29. Gain Error Due to Temperature Change vs. Frequency, 3 Sigma to Either Side of Mean, VS = 3 V, RL = 200 W, Maximum Gain
35 30 +25 C 25 20 -40 C 15 +85 C
28 23 18 13
10
3
8
OUTPUT IP3 - dBV rms
85 C 25 C
1
OUTPUT IP3 - dBm
4
40 C
-3
8
2
-5
10 5 0 10 100 FREQUENCY - MHz
3 -2 -7 1000
0
-7
-2 10 100 FREQUENCY - MHz
-9 1000
TPC 27. IP3 vs. Frequency by Temperature, VS = 5 V, RL = 200 W, Maximum Gain
TPC 30. Output P1dB vs. Frequency by Temperature, VS = 5 V, RL = 200 W, Maximum Gain
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P1dB - dBV rms
6
-1
P1dB - dBm
AD8369
60 SAMPLE FROM ONE BATCH LOT 50 30 40 40 35 SAMPLE FROM ONE BATCH LOT
PART COUNT
30
PART COUNT
3.08 3.10 3.12 GAIN STEP SIZE - dB/CODE
25 20 15 10
20
10
5 0 3.14 3.16 3.18 3.20 GAIN STEP SIZE - dB/CODE 3.22
0 3.06
TPC 31. Distribution of Gain Step Size, 70 MHz, VS = 5 V
TPC 34. Distribution of Gain Step Size, 320 MHz, VS = 5 V
18 16 14 12 SAMPLE FROM TWO BATCH LOTS
26 24 22 20 18 SAMPLE FROM TWO BATCH LOTS
PART COUNT
PART COUNT
16 14 12 10 8 6 4
10 8 6 4 2 0 -74 -73 -72 -71 -70 -69 -68 -67 -66 -65 -64 -63 -62 IMD - dBc
2 0 -58 -57 -56 -55 -54 -53 -52 IMD - dBc -51 -50 -49 -48
TPC 32. Distribution of IMD3, 70 MHz, RL = 1 kW, VOPHI - VOPLO = 1 V p-p Composite, VS = 5 V, Maximum Gain
TPC 35. Distribution of IMD3, 320 MHz, RL = 1 kW, VOPHI - VOPLO = 1 V p-p Composite, VS = 5 V, Maximum Gain
3000
1600
2500 3V, RL = 1k
1400
GROUP DELAY - ps
2000 5V, RL = 1k 1500 3V, RL = 200 1000 5V, RL = 200 500
GROUP DELAY - ps
1200
1000 ALL GAIN CODES REPRESENTED 800
600
0 0 100 200 300 400 500 FREQUENCY - MHz 600 700 800
400 0 100 200 300 400 500 FREQUENCY - MHz 600 700 800
TPC 33. Group Delay vs. Frequency by RL and Supply Voltage at Maximum Gain
TPC 36. Group Delay vs. Frequency by Gain Code, VS = 5 V, RL = 1 kW, Maximum Gain
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AD8369
100 90 80 70
PSSR - dB
60 50 40 30 20 10 0 10 100 1000 FREQUENCY - kHz 10000
TPC 37. Power Supply Rejection Ratio, VS = 5 V, RL = 1 kW, Maximum Gain
VS DIGITAL GAIN STEP SELECTION 100 3dB SWITCHED ATTENUATOR VS 100 OPLO INHI ~ CMDC 20pF INLO VS 2 - 0.7 BIAS VS/2
OPHI
Gm CELLS
FIXED GAIN
VS/2 22pF
Figure 1. General Block Diagram, Control and Signal Paths Are Differential
THEORY OF OPERATION
The AD8369 is a digitally controlled fully differential VGA based on a variation of Analog Devices' patented X-AMP architecture (Figure 1). It provides accurate gain control over a 45 dB span with a constant -3 dB bandwidth of 600 MHz. The 3 dB gain steps can be controlled by a user-selectable parallel- or serial-mode digital interface. A single pin (SENB) selects the mode. The AD8369 is designed for optimal operation when used in a fully differential system, although single-ended operation is also possible. Its nominal input and output impedances are 200 W.
Input Attenuator and Output 3 dB Step
The AD8369 is comprised of a seven-stage R-2R ladder network (eight taps) and a selected Gm stage followed by a fixed-gain differential amplifier. The ladder provides a total attenuation of 42 dB in 6 dB steps. The full signal is applied to the amplifier using the first tap; at the second tap, the signal is 6 dB lower and so on. A further 3 dB interpolating gain step is introduced at the output of the fixed gain amplifier, providing the full 45 dB of gain span.
Fixed Gain Amplifier
complementary pair of current sources, loaded with internal 100 W resistors to ac ground which provides a 200 W differential output impedance. The low frequency gain of the AD8369 can be approximated by the equation: E 200 R L E VOUT 1 = 0.6 A A VIN E 200 + R L A (15 - n) E2 where RL is the external load resistor in ohms and n is the gain code; 0 is the minimum gain code and 15 is the maximum gain code. The external load, which is in parallel combination with the internal 200 W output resistor, affects the overall gain and peak output swing. Note that the external load has no effect on the gain step size.
Input and Output Interfaces
The dc working points of the differential input and output interfaces of the AD8369 are internally biased. The inputs INHI and INLO are biased to a diode drop below VS/2 (~1.7 V for a 5 V positive supply) to meet isolation and headroom constraints, while the outputs OPHI and OPLO are centered on the supply midpoint, VS/2, to provide the maximum output swing. The internal VS/2 reference and the CMDC reference are buffered and decoupled to ground via internal capacitors. The input bias voltage, derived from this VS/2 reference, is brought
The fixed gain amplifier is driven by the tap point of the R-2R ladder network via the selected Gm cell. The output stage is a REV. 0
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AD8369
out to pin CMDC for decoupling to ground. An external capacitor from CMDC to COMM of 0.01 mF or more is recommended to lower the input common-mode impedance of the AD8369 and improve single-ended operation. Signals must be ac-coupled at the input, either via a pair of capacitors or a transformer. These may not be needed when the source has no dc path to ground, such as a SAW filter. The output may need dc blocking capacitors when driving dcgrounded loads, but it can be directly coupled to an ADC, provided that the common-mode levels are compatible. The input and output resistances form a high-pass filter in combination with any external ac-coupling capacitors that should be chosen to minimize signal roll-off at low frequencies. For example, using input-coupling capacitors of 0.1 mF, each driving a 100 W input node (200 W differential), the -3 dB high-pass corner frequency is at: shift registers are composed of four flip-flops that accept the serial data stream.
TO GAIN CONTROL SECTION BIT0 BIT1 BIT2 BIT3
GAIN CONTROL REGISTER (LATCH)
T/H DENB
MUX B A
MUX B A
MUX B A
MUX A/B B A SENB
SHIFT REGISTER
SHIFT REGISTER
SHIFT REGISTER
SHIFT REGISTER
1 = 16 kHz 2p(10 -7 )(100 )
It is important to note that the input and output resistances are subject to process variations of up to 20%. This will affect the high-pass corner frequencies and the overall gain when driven from, or loaded by, a finite impedance (see the Reducing Gain Sensitivity to Input and Output Impedance Variation section).
Noise and Distortion
BIT0 (DATA) BIT1 (CLOCK) BIT2 BIT3
Figure 2. Digital Interface Block Diagram
It is a common aspect of this style of VGAs, however implemented, that the effective noise figure worsens as the gain is reduced. The AD8369 uses a fixed gain amplifier, having a certain invariant noise spectral density, preceded by an attenuator. Thus, the noise figure increases simply by 6 dB per tap point, from a starting point of 7 dB at full gain. However, unlike voltage-controlled amplifiers that must necessarily invoke nonlinear elements in the signal path, the distortion in a step-gain amplifier can be very low and is essentially independent of the gain setting. Note that the postamplifier 3 dB step does not affect the noise performance, but it has some bearing on the output third-order intercept (OIP3). See TPCs 3 and 9.
Offset Control Loop
In parallel operation, the 4-bit parallel data is placed on pins BIT3 through BIT0 and passed along to the gain control register via the mux. Data is latched into the gain control register on the falling edge of the input to DENB, subject to meeting the specified setup and hold times. If this pin is held high (> VS/2), any changes in the parallel data will result in a change in the gain, after propagation delays. This is referred to as the transparent mode of operation. If DENB is held low, the last 4-bit word in the gain control register will remain latched regardless of the signals at the data inputs. In serial operation, the BIT0 pin is used for data input while the BIT1 pin is the clock input. Data is loaded into the serial shift registers on the rising edge of the clock when DENB is low. Given the required setup and hold times are observed, four rising edge transitions of the clock will fully load the shift register. On the rising edge of DENB, the 4-bit word in the shift register is passed into the gain control register. While this pin is held high, the clock input to the shift registers is turned off. Once DENB is taken low, the shift register clock is again enabled and the last 4-bit word prior to enabling the clock will be latched into the gain control registers. This enables the loading of a new 4-bit gain control word without interruption of the signal path. Only when DENB goes high is data transferred from the shift registers to the gain control registers. If no connections are made to the digital control pins, internal 40 kW resistors pull these pins to levels that set the AD8369 to its minimum gain condition. At power-up or chip enable, if the AD8369 is in parallel mode and DENB is held low, the gain control register will come up in an indeterminate state. To avoid this, DENB should be held high with valid data present during power-up when operating in the parallel mode. In serial mode, the data in the gain control interface powers up with a random gain code independent of the DENB pin. Serial mode operation requires at least four clock cycles and the transition of DENB from low to high for valid data to be present at the gain control register.
The AD8369 uses a control loop to null offsets at the input. If left uncorrected, these offsets, in conjunction with the gain of the AD8369, would reduce the available voltage swing at the output. The control loop samples the differential output voltage error and feeds nulling currents back into the input stage. The nominal high-pass corner frequency of this loop is internally set to 520 kHz, but it is subject to process variations of up to 20%. This corner frequency can be reduced by adding an external capacitor from the FILT pin to ground, in parallel to an internal 30 pF capacitor. For example, an external capacitor of 0.1 mF would lower the high-pass corner by a factor of 30/100,030, to approximately 156 Hz. This frequency should be chosen to be at least one decade below the lowest component of interest in the input spectrum.
Digital Control
The gain of the AD8369 is controlled via a serial or parallel interface, as shown in Figure 2. Serial or parallel operation is selected via the SENB pin. Setting SENB to a logic low (< VS/2) selects parallel operation, while a logic high on SENB (> VS/2) selects serial operation. The AD8369 has two control registers, the gain control register and the shift register. The gain control register is a latch that holds the data that sets the amplifier gain. The
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REV. 0
AD8369
VS 3V TO 5.5V 0.1 F 0.1 F 0.1 F
0.1 F 16 IN 50 TX LINE RL
15
14
13
12
11
10
9
0.1 F
INHI COMM PWUP VPOS SENB
FILT CMDC OPHI
AD8369
RL
TC4-1W INLO COMM BIT0 0.1 F 1 2 3 BIT1 4 BIT2 5 BIT3 DENB OPLO 6 7 8 0.1 F
CONTROL INTERFACE
Figure 3. Basic Connections
BASIC CONNECTIONS
Figure 3 shows the minimum connections required for basic operation of the AD8369. Supply voltages of between +3 V and +5.5 V are permissible. The supply to the VPOS pin should be decoupled with at least one low inductance surface-mount ceramic capacitor of 0.1 mF placed as close as possible to the device. More effective decoupling is provided by placing a 100 pF capacitor in parallel and including a 4.7 W resistor in series with the supply. Attention should be paid to voltage drops. A ferrite bead is a better choice than the resistor where a smaller drop is required.
Input-Output Interface
In general, there is a loss factor, 1/(1+ ), at each interface so the overall gain reduction due to source and output loading is 40 log10 (1 + ). In this case, the input and output loss factors are 0.8 (1.94 dB) at each interface so the overall gain is reduced by 3.88 dB.
Operation from a Single-Sided Source
A broadband 50 W input termination can be achieved by using a 1:2 turns-ratio transformer, as shown in Figure 3. This also can be used to convert a single-ended input signal to a balanced differential form at the inputs of the AD8369. As in all high frequency applications, the trace impedance should be maintained right up to the input pins by careful design of the PC board traces, as described in the PCB Layout Considerations section.
Reducing Gain Sensitivity to Input and Output Impedance Variation
While there are distinct benefits of driving the AD8369 with a well-balanced input, in terms of distortion and gain conformance at high frequencies, satisfactory operation will often be possible when a single-sided source is ac-coupled directly to pin INHI, and pin INLO is ac-grounded via a second capacitor. This mode of operation takes advantage of the good HF common-mode rejection of the input system. The capacitor values are, as always, selected to ensure adequate transmission at low frequencies.
VS 0.1 F 0.1 F 0.1 F
50 SOURCE
0.1 F
16
15
14
13
12
11
10
9
0.1 F
INHI COMM PWUP VPOS SENB
FILT CMDC OPHI
The lot-to-lot variations in gain mentioned previously can, in principle, be eliminated by adjustments to the source and load. Define a term as a function of the input and output resistances of the AD8369 and the source and load resistances presented to it:
RSOURCE = a (RINPUT ) ROUTPUT = a (RLOAD )
0.1 F INLO COMM BIT0 1 2 3
AD8369
RL
BIT1 4
BIT2 5
BIT3 DENB OPLO 6 7 8 0.1 F
For a 50 W source, = 0.25. Then the load resistance for zero sensitivity to variations must be 800 W. Put more simply:
CONTROL INTERFACE
(RSOURCE ) (RLOAD ) = (RINPUT ) (ROUTPUT ) = 2002
Figure 4. Single-Ended-to-Differential Application Example
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AD8369
For example, suppose the input signal in Figure 4 is a 140 MHz sinusoid from a ground-referenced 50 W source. The 0.1 mF coupling capacitors present a very low reactance at this frequency (11 mW) so that essentially all of the ac voltage is delivered to the differential inputs of the AD8369. It will be apparent that, in addition to the use of adequate coupling capacitance, the external capacitor used to extend the low frequency range of the offset control loop, CFILT, must also be large enough to prevent the offset control loop from attempting to track the ac signal fluctuations.
VS 0.1 F 0.1 F 270nH 16 15 14 13 12 11 10 9 0.1 F 0.1 F
Interfacing to an ADC
The AD8369 can be used to effectively increase the dynamic range of an ADC in a direct IF sampling receiver application. Figure 5 provides an example of an interface to an ADC designed for an IF of 70 MHz. It comprises a low-pass filter that attenuates harmonics while providing an impedance transformation from 200 W to 1 kW. This impedance transformation allows the AD8369 to operate much below its peak output swing in the pass band, which significantly reduces distortion.
INHI COMM PWUP VPOS SENB
FILT CMDC OPHI
AD8369
6.8pF
15pF
ADC
1k
INLO COMM BIT0 1 2 3
BIT1 4
BIT2 5
BIT3 DENB OPLO 6 7 8 0.1 F 270nH
CONTROL INTERFACE
Figure 5. AD8369 to ADC Interface
0 -10 -20 -30
POUT - dBFS
70MHz - 1dBFS HD2 = -83dBc HD3 = -80dBc SNR = 51dB
-40 -50 -60 -70 -80 -90
A high performance 14-bit ADC, the AD6645, is used for illustrative purposes and is sampling at 64 MSPs with a full-scale input of 2.2 V p-p. Typically, an SNR of 51 dB and an SFDR of almost -90 dBFS are realized by this configuration. Figure 6 shows an FFT of the AD8369 delivering a single tone at -1 dBFS (that is, 2 V p-p) at the input of the ADC with an HD2 of -83 dBc and HD3 of -80 dBc. Figure 7 shows that the two-tone, third-order intermodulation distortion level is -65.5 dBc.
PCB Layout Considerations
-100 0 5 10 15 20 25 ADC OUTPUT FREQUENCY - MHz 30
Figure 6. Single-Tone 70 MHz, -1 dBFS
0 -10 -20 -30
POUT - dBFS
Each input and output pin of the AD8369 presents 100 W relative to their respective ac grounds. To ensure that signal integrity is not seriously impaired by the printed circuit board, the relevant connection traces should provide a characteristic impedance of 100 W to the ground plane. This can be achieved through proper layout. Figure 8 shows the cross section of a PC board and Table II shows the dimensions that will provide a 100 W line impedance.
Table II. Dimensions Required for 100 W Characteristic Impedance Microstrip Line in FR-4
r
-7dBFS
(FR-4)
-40 -50 -60 -70 -80 -90 -72.5dBFS
W H T
4.6 22 mils 53 mils 2.1 mils
-100 0 5 10 15 20 25 ADC OUTPUT FREQUENCY - MHz 30
Figure 7. Two-Tone, 70 MHz, 70.3 MHz, -7 dBFS
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AD8369
Key considerations when laying out an RF trace with a controlled impedance include:
*
3W W 3W T
Space the ground plane to either side of the signal trace at least 3 line-widths away to ensure that a microstrip (vertical dielectric) line is formed, rather than a coplanar (lateral dielectric) waveguide. Ensure that the width of the microstrip line is constant and that there are as few discontinuations (component pads, etc.) as possible along the length of the line. Width variations cause impedance discontinuities in the line and may result in unwanted reflections. Do not use silkscreen over the signal line; this will alter the line impedance. Keep the length of the input and output connection lines as short as possible.
SW 2 3 1 2 VS C4 1nF IN J1 TC4-1W IN J2 16 15 14 13 12 C5 0.1 F C8 1nF
H
r
*
Figure 8. Cross-Sectional View of a PC Board
* *
The AD8369 contains both digital and analog sections. Care should be taken to ensure that the digital and analog sections are adequately isolated on the PC board. The use of separate ground planes for each section connected at only one point via a ferrite bead inductor will ensure that the digital pulses do not adversely affect the analog section of the AD8369.
PWUP
PWDN
R5 OPEN
C7 C8 0.1 F 1nF C2 11 10 9 1nF OUT J6 TC4-1W OUT J7
INHI COMM PWUP VPOS SENB T1 R2 0 RL
FILT CMDC OPHI R11 0 T2
AD8369
R1 0
INLO COMM BIT0 1nF C3 1 2 3 R6 0
BIT1 4 R7 0
BIT2 5 R8 0
BIT3 DENB OPLO 6 R9 0 7 R10 0 8 1nF C1
R12 0
LATCH
CLOCK
DATA C9 OPEN VS
R3 1k
R13 1k
R4 1k
2
5
8
11 SW3
SW4
4
1
3
4
6
79
10
12 1 2 4 8 A 2
VS
3 SW1
B1 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13
D-SUB 25 PIN MALE
Figure 9. Evaluation Board Schematic
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AD8369
Evaluation Board Evaluation Board Software
The evaluation board allows for quick testing of the AD8369 using standard 50 W test equipment. The schematic is shown in Figure 9. Transformers T1 and T2 are used to transform 50 W source and load impedances to the desired 200 W reference level. This allows for broadband operation of the device without the need to pay close attention to impedance matching (see Table III).
The evaluation board comes with the AD8369 control software that allows for serial gain control from most computers. The evaluation board is connected via a cable to the parallel port of the computer. By simply adjusting the slider bar in the control software, the gain code is automatically updated to the AD8369. On some older PCs, it may be necessary to use 5 kW pull-up resistors to VPOS on DATA, CLOCK, and LATCH depending upon the capabilities of the port transceiver. It is necessary to set SW3 on the evaluation board to "SER" for the control software to function normally. A screen shot of the evaluation software interface is shown in Figure 11.
Figure 10. Evaluation Board Layout
Figure 11. Evaluation Software Interface
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AD8369
Table III. AD8369 Evaluation Board Configuration Options
Component VPOS, GND SW1 SW2
Function Supply and Ground Vector Pins Data Enable: Set to Position A when in serial mode of operation, set to Position B when in parallel mode of operation. Device Enable: When in the PWDN position, the PWUP pin will be connected to ground and the AD8369 will be disabled. The device is enabled when the switch is in the PWUP position, connecting the PWUP pin to VPOS. Serial/Parallel Selection. The device will respond to serial control inputs from connector P1 when the switch is in the SER position. Parallel operation is achieved when in the PAR position. Device can be hardwired for parallel mode of operation by placing the 0 W resistor in position R5. Parallel Interface Control. Used to hardwire BIT0 through BIT3 to the desired gain code when in parallel mode of operation. The switch functions as a hexadecimal to binary encoder (Gain Code 0 = 0000, Gain Code 15 = 1111). Input and Output Signal Connectors. These SMA connectors provide a convenient way to interface the evaluation board with 50 W test equipment. AC-Coupling Capacitors. Provides ac-coupling of the input and output signals. Impedance Transformers. Used to transform the 200 W input and output impedance to 50 W. Single-Ended or Differential. R2 and R11 are used to ground the center tap of the secondary windings on transformers T1 and T2. R1 and R12 should be used to ground J2 and J7 when used in single-ended applications. R1 and R12 should be removed for differential operation.
Default Condition Not Applicable Not Applicable Not Applicable
SW3, R5
Not Applicable R5 = Open (Size 0603)
SW4
Not Applicable
J1, J2, J6, J7 C1, C2, C3, C4 T1, T2 R1, R2, R11, R12
Not Applicable C1, C2, C3, C4 = 1 nF (Size 0603) T1, T2 = TC4-1W (MiniCircuits) R1, R2, R11, R12 = 0 W (Size 0603)
R6, R7, R8, R9, R10 Control Interface Resistors. Simple series resistors for each control interface signal. C5, C6, C8 Power Supply Decoupling. Nominal supply decoupling consists of a 0.1 mF capacitor to ground followed by a 1 nF capacitor to ground positioned as close to the device as possible. C8 provides additional decoupling of the input common-mode voltage. High-Pass Filter Capacitor. Used to set high-pass corner frequency of output. Clock Filter Capacitor. May be required with some printer ports to minimize overshoot. The clock waveform may be smoothed using a simple filter network established by R7 and C9. Some experimentation may be necessary to determine optimum values.
R6, R7, R8, R9, R10 = 0 W (Size 0603) C5 = 0.1 mF (Size 0603) C6 = C8 = 1 nF (Size 0603) C7 = 0.1 mF (Size 0603) C9 = Open (Size 0603)
C7 C9
REV. 0
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AD8369
APPENDIX Characterization Equipment Composite Waveform Assumption
Two sets of automated characterization equipment were used to obtain the majority of the information contained in this data sheet. An Agilent N4441A Balanced Measurement System was used to obtain the gain, phase, group delay, reverse isolation, CMRR, and s-parameter information. Except for the s-parameter information, T-attenuator pads were used to match the 50 W impedance of the ports of this instrument to the AD8369. An Anritsu MS4623B "Scorpion" Vector Network Analyzer was used to obtain nonlinear measurements IMD3, IP3, and P1dB through matching baluns and attenuator networks.
Definitions of Selected Parameters
The nonlinear two-tone measurements made for this data sheet, i.e., IMD3 and IP3, are based on the assumption of a fixed value composite waveform at the output, generally 1 V p-p. The frequencies of interest dictate the use of RF test equipment and because this equipment is generally not designed to work in units of volts, but rather watts and dBm, an assumption was made to simplify equipment setup and operation. Two sinusoidal tones can be represented as: V2 = sin (2p f2 t ) The average voltage of one tone is: 1T 1 2 V U ( 1 ) dt = T0 2 where T is the period of the waveform. The average voltage of the two-tone composite signal is:
1T 2 V U ( 1 + V2 ) dt = 1 T0
V1 = sin (2p f1 t )
Common-mode rejection ratio (TPC 14) has been defined for this characterization effort as:
Differential - Mode, forwardgain Common - Mode, forwardgain
where the numerator is the gain into a differential load at the output due to a differential source at the input and the denominator is the gain into a common-mode load at the output due to a common-mode source at the input. In terms of mixed-mode s-parameters, this equates to: SDD 21 SCC 21 Reverse isolation (TPC 17) is defined as SDD12. More information on mixed-mode s-parameters can be obtained in the a reference by Bockelman, D.E. and Eisenstadt, W.R., Combined Differential and Common-Mode Scattering Parameters: Theory and Simulation. IEEE Transactions on Microwave Theory and Techniques, v 43, n 7, 1530 (July 1995).
VS 0.1 F 10nF
So each tone contributes 1//2 to the average composite amplitude in terms of voltage. It can be shown that the average power of this composite waveform is two times greater, or 3dB, than that of the single tone. This principle can be used to set correct input amplitudes from generators scaled in dBm and is correct if the two tones are of equal amplitude and are not farther than 1 percent apart in frequency.
0.1 F
1nF
RL= 200 DIFFERENTIAL: R1 = 69.8 , R2 = 69.8 RL= 1000 DIFFERENTIAL: R1 = 475 , R2 = 52.3 10nF R1
69.8
69.8
10nF
16
15
14
13
12
11
10
9
R2
INHI COMM PWUP VPOS SENB
FILT CMDC OPHI
RL
AD8369
INLO COMM BIT0 1 69.8 69.8 10nF 2 3
BIT1 4
BIT2 5
BIT3 DENB OPLO 6 7 8 10nF R1 R2
CONTROL INTERFACE
PORT1
AGILENT N4441A (ALL PORTS 50 )
PORT2
PORT3
PORT4
Figure 12. Balanced Measurement System Setup
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AD8369
VS 0.1 F 10nF 0.1 F 1nF
10nF MINI-CIRCUITS TC4-1W
16
15
14
13
12
11
10
9
10nF MINI-CIRCUITS TC4-1W
INHI COMM PWUP VPOS SENB
FILT CMDC OPHI
RL
AD8369
INLO COMM BIT0 1 10nF 2 3
BIT1 4
BIT2 5
BIT3 DENB OPLO 6 7 8 10nF
CONTROL INTERFACE
ANRITSU MS4623B VNA SOURCE OUTPUT RECEIVER INPUT
Figure 13. Vector Network Analyzer Setup (200 W)
VS 0.1 F 10nF 0.1 F 1nF
10nF MINI-CIRCUITS TC4-1W
16
15
14
13
12
11
10
9
10nF
604 MINI-CIRCUITS TC4-1W
INHI COMM PWUP VPOS SENB
FILT CMDC OPHI
AD8369
4120
237
INLO COMM BIT0 1 10nF 2 3
BIT1 4
BIT2 5
BIT3 DENB OPLO 6 7 8 10nF 604
CONTROL INTERFACE
ANRITSU MS4623B VNA SOURCE OUTPUT RECEIVER INPUT
Figure 14. Vector Network Analyzer Setup (1 kW)
REV. 0
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AD8369
VS 5.0V 0.1 F 1nF 0.1 F 100nF 100nF -19dB 100nF MACOM ETC1-1-13 100nF -12dB 100nF VS 100nF TEK 1103 PROBE POWER SUPPLY AD8351 191 100nF 162 113 191 162 113 TEK P6248 DIFF PROBE 16 15 14 13 12 11 1nF 10 9 100nF
INHI COMM PWUP VPOS SENB
FILT CMDC OPHI
AD8369
RL
LPF
INLO COMM BIT0 1 2 3
BIT1 4
BIT2 5
BIT3 DENB OPLO 6 7 8
RF OUT R & S SMT-03 SIGNAL GENERATOR
R&S FSEA30 SPECTRUM ANALYZER
Figure 15. Harmonic Distortion Setup
R & S SMT-03 SIGNAL GENERATOR RF OUT
VS 5.0V
0.1 F
1nF
0.1 F
1nF
-34dBm AT 70MHz 10nF 16 15 14 13 12 11 10 9 10nF INHI COMM PWUP VPOS SENB FILT CMDC OPHI
604 AGILENT INFINIUM DSO
MINI-CIRCUITS TC4-1W
RL
AD8369
4120
237
MINI-CIRCUITS TC4-1W
INLO COMM BIT0 1 10nF 50 PICOSECOND PULSE LABS PULSE GENERATOR 2 3
BIT1 4
BIT2 5
BIT3 DENB OPLO 6 7 8 10nF 604
VS
Figure 16. Gain Step Response Setup
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AD8369
AGILENT 8112A PULSE GENERATOR SPLITTER TEK TDS 5104 DSO
2F R & S SMT-03 SIGNAL GENERATOR RF OUT PULSE IN 0.1 F 10nF 16 15 14 13 12
10 F
VS 5.0V
1nF 10 9 100nF
11
INHI COMM PWUP VPOS SENB
FILT CMDC OPHI TEK 1103 PROBE POWER SUPPLY
MINI-CIRCUITS TC4-1W
0
AD8369
1000
TEK P6248 DIFF PROBE
0 INLO COMM BIT0 10nF C2 1 2 3 BIT1 4 BIT2 5 BIT3 DENB OPLO 6 7 8 100nF VS
Figure 17. Pulse Response Setup
R & S SMT-03 SIGNAL GENERATOR RF OUT -20dBm AT 10MHz
VS 5.0V
0.1 F
1nF
0.1 F
1nF
10nF
16
15
14
13
12
11
10
9
10nF
604 AGILENT INFINIUM DSO
INHI COMM PWUP VPOS SENB
FILT CMDC OPHI
MINI-CIRCUITS TC4-1W
RL
AD8369
4120
237
MINI-CIRCUITS TC4-1W
INLO COMM BIT0 1 10nF 2 3
BIT1 4
BIT2 5
BIT3 DENB OPLO 6 7 8 10nF 604
PICOSECOND PULSE LABS PULSE GENERATOR
VS 50
Figure 18. Overdrive Response Setup
REV. 0
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AD8369
OUTLINE DIMENSIONS 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16)
Dimensions shown in millimeters
5.10 5.00 4.90
16
9
4.50 4.40 4.30
1 8
6.40 BSC
PIN 1 1.20 MAX 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8 0 0.75 0.60 0.45
0.15 0.05
COMPLIANT TO JEDEC STANDARDS MO-153AB
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PRINTED IN U.S.A.
C03029-0-11/02(0)

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